Integrated circuits have achieved widespread use in that they are capable of reducing the space required to achieve a given electrical function, with an attendant increase in performance including a reduction in power requirements. In order for integrated circuits to conveniently interface with other integrated circuits and other types of electronic circuitry, certain industry-wide input/output (I/O) specifications have been developed. One example is the transistor-transistor logic (TTL) standard in which a supply voltage of five volts (nominal) is applied to a device. An input signal associated with a logical zero has a maximum voltage of approximately 0.7 volts and a logical one input level has a minimum voltage of approximately two volts. This TTL specification also requires that an integrated circuit provide an output voltage of at least approximately 2.4 volts associated with a logical one output signal, and an output voltage of not more than approximately 0.4 volts associated with a logical zero output level.
Current advancements in integrated circuit technology are spurring an evolution to lower voltage devices than the TTL standard. For example, one current trend is to develop integrated circuits utilizing 3 or 3.3 volt power supplies. In the future, even lower voltage devices (such as 2.4 volt devices) will be developed. Among the reasons for moving to lower voltage integrated circuits are a need to reduce system power without a corresponding tradeoff in performance.
Given the large number of TTL device types, it would be desirable to provide lower voltage devices which are capable of withstanding excessive voltages applied to their input and output pins from external sources, for example, if they are inadvertently or intentionally used with TTL devices or interfaces. Thus, for example, for a 3.0 volt device in which a high output voltage of approximately three volts corresponds to a logical one output signal, it would be very beneficial if the device were able to withstand a TTL logical one voltage level of approximately 5 volts applied to the output terminal, without consuming excessive power or incurring damage. Similarly, it would be very beneficial if a 2.4 volt device were able to withstand a logical one level of approximately 5 volts (TTL standard) or approximately 3.0 volts (for a 3.0 volt device) logical one signals apply to the output terminal.
FIGS. 1-8 are prior art input and output circuits which are known in the art. The following discussion describes the merits or lack thereof in using each of these input/output circuits in conjunction with an integrated circuit operating at a supply voltage VCC level of, for example, 3.3 volts.
FIG. 1 is a schematic diagram depicting a typical CMOS input stage. Input pad 10 receives an input signal from external circuitry for application to input buffer 13, whose output is connected to other circuitry (not shown) within the integrated circuit. Input protection diodes 11 and 12 are used in order to provide overvoltage protection for input pad 10. Input protection diode 11 forward biases when the input voltage is greater than VCC+VD, where VD is the forward bias voltage drop of input protection diode 11. Thus, when VCC is 5 volts, as in the prior art, input pad 10 is protected from voltage excursions exceeding approximately 5.6 volts. However, when VCC is 3.3 volts, and a 5 volt TTL level is applied to input pad 10, input protection diode 11 turns on, thereby providing input overvoltage protection while drawing an intolerable amount of current in a situation in which an acceptable 5 volt level is applied to input pad 10.
FIG. 2 is a schematic diagram of a typical CMOS output stage including output pad 20, output pad overvoltage protection diodes 21 and 22, pull up transistor 23, and pull down transistor 24. With a 3.3 volt power supply voltage, and an acceptable 5 volt TTL level applied externally to output pad 20, output protection diode 21 forward biases, undesirably pulling down pad 20 to 3.3 volts and consuming excessive current in the process. Furthermore, in the circuit of FIG. 2, with a 5 volt level applied to output pad 20 and the gate of P channel pull up transistor 23 being not more than three volts, P channel pull up transistor 23 turns on, causing excessive current to flow from output pad 20 through pull up transistor 23.
FIG. 3 is a schematic diagram of another prior art output stage including output pad 30, P channel pull up transistor 33, N channel pull down transistor 35, and Schottky diode 35. However, if this prior art 5 volt output stage were used with lower voltage circuits, for example with a 3.3 volt circuit in which the power supply may drop as low as 2.7 volts, the output high level applied by this circuit to output pad 30 would not be sufficiently high due to the voltage drop across Schottky diode 35. Schottky diodes used in I/O circuits tend to be very susceptible to damage due to electrostatic discharge (ESD). Furthermore, CMOS fabrication processes often do not allow for the fabrication of Schottky diodes, and this circuit must therefore be limited to use in BiCMOS devices, which are inherently more complex and expensive than CMOS processes.
FIG. 4 is a schematic diagram of another prior art BiCMOS output stage including output pad 40, P channel pull up transistor 43, N channel pull down transistor 44, and Schottky diode 46 coupled between the source and well region of P channel pull up transistor 43. Schottky diode 46 connected in this manner prevents the inherent diode formed between the drain and the well region of P channel pull up transistor 43 from forward biasing. However, this allows the well region of P channel transistor 43 to float between the supply voltage and a diode drop below the supply voltage level, which is undesirable in that floating wells are more susceptible to latch up and unpredictable performance. Also, this circuit will not prevent leakage through P channel transistor 43 when an externally applied voltage to output pad 40 exceeds its gate voltage. Other prior art variations on this circuit cause the well region of P channel pull up transistor 43 to be switched to a specific voltage level, for example by the use of field transistors. However, unless a well region is connected via a low impedance path to a fixed voltage level, latch-up is a distinct possibility. Field Effect Transistors, which are typically used for switching purposes, including possibly switching the well region of P channel pull up transistor 43, have relatively high resistance, thereby increasing the possibility of latch-up. Furthermore, this output circuit cannot be used in CMOS devices as most CMOS processes do not support the fabrication of Schottky diodes.
FIG. 5 is a schematic diagram of a prior art MOS output stage utilizing both an N channel pull up transistor 53 and an N channel pull down transistor 54. However, the use of an N channel pull up transistor 53 at lower voltages, such as with a 3.3 volt power supply level, does not provide sufficient over- drive to provide a sufficiently high output voltage level on output pad 50.
FIG. 6 is a prior art MOS output stage similar to that of FIG. 5 which overcomes the problems of FIG. 5 by utilizing a separate diffusion mask to provide a lower threshold voltage for N channel pull up transistor 63 than is provided for other N channel transistors in the device, including pull down transistor 64. This provides a greater amount of overdrive, even when using low voltages such as a 3.3 volt power supply voltage. However, this prior art device has the significant disadvantage of requiring a separate diffusion mask, thereby increasing the number of steps required to fabricate this device and adding a significant amount to fabrication cost.
FIG. 7 is a schematic diagram of a prior art bipolar output stage used in certain BiCMOS devices. When used with a low voltage device, such as a device using a 3.3 volt power supply, NPN pull up transistor 73 does not provide a sufficiently high output voltage level on output pad 70. It has been suggested that an additional PNP transistor or P channel device 75 be used as shown in order to provide an increase in output voltage on output pad 70. However, this device requires the use of bipolar transistors, and thus cannot be used in a pure MOS device, but will require the additional expense of a BiCMOS device, and will still have the problems associated with the use of a P channel pull up device.
FIG. 8 is a schematic diagram of a CMOS output stage which can be used with low voltage devices. In this prior art output stage, the gate oxide for output transistors 83 and 84 is approximately 150.ANG. while the gate oxide for other transistors in the integrated circuit, such as exemplified by buffer 89, is approximately 110.ANG.. This serves to improve the reliability of the output stage, in that output transistors, which may see a relatively high externally applied voltage, have thicker gate oxides which are better capable of withstanding the externally applied high voltage. However, this does not solve the problem of P channel pull up transistor 83 conducting when an externally applied voltage to output pad 80 exceeds the supply voltage of the device, for example when the device is powered by 3.3 volts and an external 5 volts is applied to output pad 80. Furthermore, output transistors 83 and 84 must be made larger since their channel lengths must be increased with increasing gate oxide thicknesses. Perhaps an even greater problem is the fact that this process is complex, and therefore expensive, in that at least two separate masks are required to achieve two separate gate oxide thicknesses in a single integrated circuit.
The disadvantage of requiring two separate gate oxide thicknesses can be overcome, of course, by using a 150.ANG. gate oxide for the entire integrated circuit. However, this will increase the die size as devices must be made larger (with increased channel lengths) with increasing gate oxide thicknesses. Also, thicker gate oxides result in a reduction in speed. Furthermore, this circuit could be used with a 3.3 volt supply powering the internal logic of the integrated circuit and a 5 volt supply powering the output buffer. However, this will either require two separate external supplies, or will require the 3.3 volt supply to be internally generated on chip from the externally applied 5 volt supply. This consumes power, and integrated circuit die area, and leads away from the desire to provide integrated circuits which operate with lower voltage supplies.